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27號(hào)補(bǔ)丁修復(fù)的BUG較多！
7 Y0 e; `% O2 \: I& Q' }百度網(wǎng)盤下載鏈接http://pan.baidu.com/s/1mgwSsPy5 F' ~5 q8 E& ~6 _# D+ C2 o
) W, j2 B. ^( @& lDATE: 04-25-2014 HOTFIX VERSION: 027
1 ~* ?" V# d9 ^( i===================================================================================================================================5 R+ P! m! C0 Q3 {) z
CCRID PRODUCT PRODUCTLEVEL2 TITLE
9 \. c e# |% z+ K6 I6 v& B===================================================================================================================================
- v5 m. h g( ]& q. B. P308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM/ j+ `$ e) h2 D0 t
481674 allegro_EDITOR pads_IN No board file saved from pads_in
; u1 o% ]) `5 v5 m; M7 H3 B982929 allegro_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin./ \' |% u( ?9 P- o* j
1012783 FSP OTHER Need Undo Command in FSP0 E% f/ _6 {0 b; L& E
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
' _! N3 w3 P8 l( P$ V+ J1072673 pcb_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved, g* m9 g! u6 U& |- c: S
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.% d. ^' O- r$ [$ ?) w- ~5 Q
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
* o2 u, S5 e! }# m9 H: L& q1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash" R8 Y9 @9 R" C$ M0 v! ~
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
: W# q' u( q' m2 Y' `: F1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode" Q" n4 g7 R+ {
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present# G. g. o$ U. z& @
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
* `, S; V0 R+ t. e3 J1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings$ K4 {+ D8 c' h6 J
1185575 SIP_layout DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
! F: c) a+ I9 V1 H# E) T1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
7 `* O# x/ `/ }! n/ Q1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.* ~- s+ U( S9 q+ i$ n
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
) n; r3 C6 [* a7 }$ h* T u1 T1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
3 A8 n* A. v2 X5 K# d1208478 PSPICE PROBE Attached project gives overflow error with marching ON.. |8 d* ~/ ^5 ~( J$ u* l9 P/ \4 ?
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
# e; E; f X0 d1 s& V" p( _1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
$ m+ r& \3 ~/ J _+ a( o; p1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
- k9 N' ~% d; J% }# @1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
1 A K* Y+ l; w3 k) C, o( T1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
t+ O' A2 C: s- z1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.7 K7 J- h# o5 z1 w6 K9 U+ T
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values5 P; O+ V% F0 u, p
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging! L# m$ w* x3 u+ ], q- O
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information r9 [' x- x3 W9 r, r
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added9 d$ z. t. r: A- E
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.# V3 ]) r; e# E. `) B4 E
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
- s# y" t- p% K; X# H: P1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
. U! Q+ ?: Q6 m+ _, L8 [- {1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
& }: \2 |$ W% ]- C6 n1221182 ADW TDA Team Design with SAMBA/ v, C ?' Y+ o; _# q# c& y
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair0 d' |7 M" ~: c& A4 i
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
_8 }9 u3 i& `, X9 \) y1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
$ w; _- V2 j/ p, ~) n- I/ Z1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
: ]& @2 ?5 s' f o2 N! L, `1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms# b2 m* Z5 Y: | E/ y$ n0 S/ k: b
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
# ~# I( y" {- u# N5 t/ T1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor8 e1 v X# W% m7 O
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
# M+ \' U& c: j1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path3 m' w: ^1 E0 I
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin" c7 w/ q2 W x4 Z0 K
1225494 CAPTURE DRC Different DRC results for Entire design and selection/ X6 M' q! c% y1 p: _
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
) X7 o& ^5 E) k: ]% Q, t1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
& y8 Z* z" J7 {" Z% H! M, Y& |+ k1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet7 M7 v! C% D; r, @+ x, n6 C$ `
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
8 n1 r) p: {0 C* u, Z! J2 b6 S1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file1 U7 g' E; f. c- i+ }
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
2 z6 J! r" J. f0 p. W1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
( M$ s0 |3 n: Q: C8 m' \- G; B% [, Y; z. P1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration) l9 y. R0 U7 _( b. Q3 l9 B
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
Z9 P: q5 z, \& T, M1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
- k7 p( p: D- u% i3 o, k1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
; r. j/ ?5 Z, X1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
: H" A8 ^4 r4 \% a1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
% P( [$ b; ?/ _8 ?1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility., b+ i& `, R6 {$ @* _7 S3 y
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
& k. f' E& I j# l- F4 x1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
- U" {, l( K* {& u7 e9 P( I% b1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
) J' K. ^2 ^3 D+ t7 S1230432 CONCEPT_HDL CORE No Description information in BOM
' {/ w, Y: i1 M8 z* p0 m& j1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
- I8 }& K* a! ^5 I2 V% O1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files+ S+ [" e% b6 j6 ^6 y& b, h
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
) m3 \8 [2 u4 A; w5 t1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
: b$ a* e, `3 T, M, a( P* g2 V1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board." ~ ?+ k' [1 y8 m+ o) e0 j! Q
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode
2 D; [0 w# b# ?3 x* }4 S4 B1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical5 t* t4 J. |* b8 e5 l" a2 p. a
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode3 L+ Q) t! ^+ n/ s3 H# u% U
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
# H3 s+ c b- J% V3 I3 Q! D) I1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy! E9 u: P+ p* C! ]6 k
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
8 s7 R s) b. t1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect& d! J; }0 o1 Q3 C
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
! l0 T3 i7 B' F) e: |* g3 t1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic9 z0 M; l/ C/ E* p" t# \& K
1236161 CONCEPT_HDL CORE Import Design shows the current project pages8 v; ~$ y. X9 I" y' |. R' X
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances./ C+ m. s5 r& n3 F7 q
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
9 [; x! I+ e. H P1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file+ e( ~" k8 l9 | u" K
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape8 b9 m* g1 j k5 k+ A2 W
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
: @( W: b# w w/ r1236781 F2B PACKAGERXL Export Physical produces empty files6 {3 W1 b8 }" @
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run, a0 ^' V; h4 r3 k
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command; M2 |; Y% W1 ?) a8 J) `2 |
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition1 `3 H- B8 h8 r. z U
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
& ]- ~+ A7 f6 t! j" V1238852 CAPTURE GENERAL signal list not updated for buses& y0 |( S8 Q. s- D9 B
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes% B/ q0 u. q6 y
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
6 Z$ H* U/ `' V* |' I- B1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
) y$ n+ w* N+ H. s% c$ _- w1239763 PSPICE PROBE Cannot modify text label if right y axis is active
7 O/ P0 V( J. \, {7 C1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
3 g- f; z! D, n) [! j6 b6 [) T6 V1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.! H) m. w# w# e& r
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
7 P9 _' Z- [$ m, t% J' X! h$ g1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
; v3 [! R: r5 e: t/ B1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
6 U& S/ h) {. [- M8 S1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
" `2 W; f+ G3 ?1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms$ k; G- [8 p. i: V: V9 c- y
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
+ L+ r& q0 ^+ ~( }0 `1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
, S6 g: {; | {8 F& c; x1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard- U8 E& v2 R6 m3 q
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning$ Y0 k6 K& ` D3 J# a
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
$ E, e& n: O# I/ n1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer) l5 x0 d! l2 y7 f7 A& G
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results9 B* Z6 G- t" s
1243609 CONCEPT_HDL CORE autoprop for occurrence properties' n4 @3 {+ G- V8 G
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
6 B: [- S+ i% j3 O. a' A \1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
" j% Q$ J |8 J+ q; H; a, H% X1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
7 c* b/ E' [* X% |7 ^1 k+ o1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
) T; K5 n/ i, x! k$ D& T, z8 Q* y1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is7 M' l H% J& R7 @
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design) G/ K3 i5 P4 ?# ?& k0 S
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?, G+ _& E3 s& e
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character0 C. f* E) G! u7 x, @
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters4 D# [3 [6 X, |1 w Z
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
# d/ [6 h# E0 k; w0 _1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
" Q; h8 r, d# e1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
+ y0 z8 l' d0 V3 j5 Y4 ?- p1 P1 f' V1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained8 q. s2 C( B, t* N, }7 ?7 r
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box7 V4 J* g# a2 X: `0 H' l, M
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered. m) E8 F& z/ `# b9 a9 b
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
. {8 f. p3 M, z7 R1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
0 n, R R9 c, |. V# M1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
1 ~4 T( N$ e' l' }: K. d& ~8 q1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
$ K3 H1 E7 `3 v# [, E/ y1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly2 b( t, ]# y8 p6 C8 N) h
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
& m: K0 Q$ F# `6 d* p1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
: p! P2 S7 V7 c1253424 SCM SCHGEN Export Schematics Crashes System Architect# ~3 x, P/ p6 J
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled- r. g- v5 N+ A: W1 H8 \# U
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
. J5 E; Y! B' c7 l i. K( G, k/ ]9 G2 R i1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
8 w# O7 ~ S/ y# B+ G: \0 p8 P' P1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
% e( W4 w5 Z% f! d4 B1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.9 m& q- |! K+ g( z) h
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation% b7 ~: e$ p* J* l
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects5 L; s2 H0 d* g2 v% g0 h2 I
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
d* F6 Y; [0 C0 z- l1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
, l: W2 h+ u' d; M7 r m1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE* ~1 l2 K/ E- Q7 s9 m4 o
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
' O# @. S/ n9 D: j% M1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design- |7 }. y ?1 T$ |8 i' ?1 T$ U* d
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library9 p: h5 Q- r( r$ d; H- c
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
5 }2 t* _2 z- R2 ~+ Q+ h1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
$ g) l8 r+ f# j$ ?% ]6 \1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
% E* [$ G" ?( O2 D! R( q1258029 APD WIREBOND The bondwire lost after import the wire information: M. O& l- J% a$ I
1258979 APD NC NC Drill: There is difference of number of drills.( `9 \7 F( M+ p% D* y
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
; v- R+ ?2 t! i6 N7 q1 m- ]0 e1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
$ `, q5 s& Q8 A9 Q+ R1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
3 F9 y* E% Q. ~. E1 N% D9 U1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines+ L: a& `/ R$ h( B0 G* w. R
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
( | o! q# a4 r5 `8 ?9 S0 d1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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