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Switch mode regulators
; L3 g1 ~: O3 {( VQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators: U3 {, x: p' T; M
receive power from VBAT or VCHG under application software control.
- b: \" Q5 Z: m* k" K! P% qThe System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC30408 i2 N, E/ r6 {
VFBGA and the flash memory. The System SMPS can supply power to external components.
# ~! R- B8 A& v' \The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches. x+ }9 v/ U; w8 H( @/ [
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.' _0 l% R7 D* G9 ^& o$ _& r. J2 b
The SMPS both have three operating modes:- Z+ \* e& A% |7 {5 R
■ Normal (PWM)# b) D. t: [3 e1 F& ~" u3 g D% U" x
■ Two low-power modes with reduced current capability:
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□ ULP" T0 a" W5 d4 `! h
Normally the system auto switches, but this is optionally disabled.0 w9 y5 C/ ?0 \
The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
& h) V3 D& k- tFor guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-. }/ U |4 ]! g0 G5 O4 x# V
CH285-1).5 K' S( r' g2 Q& ~4 ]2 S6 p+ L8 v
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have; q8 u8 ^( E: Q& }8 y1 {2 Q, }
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.$ I& `$ h2 k: V. W% I( e' s8 | ]4 O
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
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